1. Field of the Invention
This invention relates to a method of testing a connection condition of input and output terminals of a plurality of integrated circuits constituting an electronic apparatus.
2. Description of the Related Art
Conventional integrated circuits typically have, as shown in FIG. 12, a plurality of parallel input terminals PI and parallel output terminals PO for data as well as a serial interface SIF by way of which serial communication is performed with a microcomputer or another integrated circuit (IC). The serial interface SIF includes a serial input terminal SI for data, a serial output terminal SO for data, a clock terminal SCK for communication, and a chip select terminal CS for selection of the integrated circuit. In actual integrated circuits, however, the parallel input terminals PI and the parallel output terminals PO are not always arranged regularly in this manner, and some integrated circuits have terminals which are used for both of inputting and outputting operations. Some other integrated circuits have no parallel input terminals. In FIG. 12, the integrated circuit is shown constructed in such a manner as described above only for simplification of description.
When a plurality of such integrated circuits are connected to each other, as shown in FIG. 13, the parallel output terminals PO of a first integrated circuit ICA are connected to the parallel input terminals PI of a second integrated circuit ICB, and the serial input terminals SI, the serial output terminals SO and the clock terminals SCK of the serial interfaces SIF of the integrated circuits ICA and ICB are connected commonly, respectively. Meanwhile, the chip select terminals CS of the integrated circuits ICA and ICB are connected separately from each other to a controlling microcomputer COM so that the microcomputer COM may select the other party of communication by way of the chip select terminals CS to perform time-division communication.
By the way, when a plurality of integrated circuits of the type described above are connected to each other so as to communicate data with each other, it must necessarily be tested whether or not the parallel input terminals PI and the parallel output terminals PO of the integrated circuits are individually connected with certainty. Particularly where a large number of integrated circuits are arranged in a high density on a circuit board of a limited area, wiring processing is complicated, resulting in a problem that it is further difficult to test a connection condition of the wiring lines with certainty.
One solution to this problem is a testing method called boundary scan, which is disclosed, for example, in IEEE Std 1149.1-1990, May 21, 1990. Referring to FIG. 14, an integrated circuit IC11, which is constructed so as to allow the boundary scan, has, in addition to parallel input terminals PI and parallel output terminals PO for data and a serial interface SIF for serial communication, a test interface TIF for boundary scan.
The test interface TIF includes a test serial input terminal TSI for serially inputting data from the outside, a test serial output terminal TSO for outputting inputted test data serially, a test clock input terminal TCK for inputting a clock signal for processing of test data, and a test mode select terminal TMS for inputting an instruction to set the integrated circuit IC11 to a test mode.
Referring now to FIG. 15, the integrated circuit IC11 has, in the inside thereof, boundary scan (S/C) cells BC1 to BC4 corresponding to the input terminals PI1 to PI4 of the parallel input terminals PI between the parallel input terminals PI and a function logic circuit FLG for executing predetermined data processing. Further, boundary scan (S/C) cells BC5 to BC8 are provided corresponding to the output terminals PO5 to PO8 of the parallel output terminals PO between the parallel output terminals PO and the function logic circuit FLG. It is to be noted that the test clock input terminal TCK and the test mode select terminal TMS are omitted in FIG. 15.
FIG. 16(a) shows an exemplary detailed construction of the boundary scan cells BC1 to BC4 of FIG. 15 while FIG. 16(b) shows an exemplary detailed construction of the boundary scan cells BC5 to BC8.
Referring first to FIG. 16(a), data inputted by way of an input terminal PIi (in the arrangement shown in FIG. 15, i is an integer from 1 to 4) is sent out to the function logic circuit FLG and a first input of a multiplexer MUX. Output data from a boundary scan cell at a preceding stage (that is, input data to the test serial input terminal TSI when the boundary scan cell shown is the boundary scan cell BC1, but when the boundary scan cell shown is any of the other boundary scan cells BC2 to BC4, output data from a preceding one of the boundary scan cells BC1 to BC3, respectively) is inputted to a second input of the multiplexer MUX. When the multiplexer MUX is set to a test mode, it fetches data from the input terminal PIi and outputs it to a D-type flip-flop D-FF, but when a signal "SHIFT DR" is inputted to the multiplexer MUX, the multiplexer MUX outputs data received from the boundary scan cell at the preceding stage to the D-type flip-flop D-FF. Then, when a clock signal CLOCK DR is sent out to the D-type flip-flop in this condition, the output of the D-type flip-flop D-FF is transferred to the boundary scan cell at the next stage.
Referring now to FIG. 16(b), data inputted from the function logic circuit FLG is inputted to a first input of a multiplexer MUX. Meanwhile, data inputted from a boundary scan cell at a preceding stage is inputted to a second input of the multiplexer MUX by way of a D-type flip-flop D-FF. When the multiplexer MUX is set to a test mode, the output of the D-type flip-flop D-FF is sent out to an output terminal POj (in the arrangement of FIG. 15, j is an integer from 5 to 8), but in an ordinary operation mode, data inputted from the function logic circuit FLG is sent out to the output terminal POj. The output of the D-type flip-flop D-FF is outputted also to a next stage (that is, to the test serial output terminal TSO when the boundary scan cell shown is the boundary scan cell BC8, but when the boundary scan cell shown is any of the other boundary scan cells BC5 to BC7, to a following one of the boundary scan cells BC6 to BC8, respectively).
It is to be noted that, though not shown, the integrated circuit IC11 of FIG. 15 includes circuits for generating and sending out a signal "SHIFT DR" and a clock signal CLOCK DR to the boundary scan cells and an ordinary signal processing circuit for processing, in an ordinary operation mode, data inputted by way of the serial interface SIF to perform setting of a mode of the function logic circuit FLG, setting of a parameter and so forth.
In a test mode, the integrated circuit IC11 constructed in such a manner as described above operates in the following manner.
1. Serial data of 4 bits inputted by way of the test serial input terminal TSI is stored once into the boundary scan cells BC1 to BC4 and then transferred to the boundary scan cells BC5 to BC8, respectively, in response to a clock signal CLOCK DR, whereafter it is outputted by way of the test serial output terminal TSO.
2. Data of 4 bits inputted parallelly by way of the input terminals PI1 to PI4 is stored once into the boundary scan cells BC1 to BC4 and then transferred to the boundary scan cells BC5 to BC8, respectively, in response to a clock signal CLOCK DR, whereafter it is outputted as serial data by way of the test serial output terminal TSO.
3. Serial data of 4 bits inputted by way of the test serial input terminal TSI is stored once into the boundary scan cells BC1 to BC4 and then transferred to the boundary scan cells BC5 to BC8, respectively, in response to a clock signal CLOCK DR, whereafter it is outputted as parallel data by way of the corresponding output terminals PO5 to PO8, respectively.
The integrated circuit IC11 having the test interface TIF and the boundary scan cells BC1 to BC8 in this manner and integrated circuits IC12 to IC14 having a similar construction are connected to each other in such a manner as shown in FIG. 17, and test data TD in the form of serial data of 4 bits for testing is inputted to the test serial input terminal TSI of the first integrated circuit IC11. The test data TD is stored into the boundary scan cells BC5 to BC8 provided on the parallel output terminals PO side of the integrated circuit IC11 shown in FIG. 15, and then outputted from the parallel output terminals PO to the input terminals PI of the second integrated circuit IC12 connected to the corresponding parallel output terminals PO of the first integrated circuit IC11.
The test data TD inputted to the parallel input terminals PI of the second integrated circuit IC12 is stored into the boundary scan cells (similar to the boundary scan cells BC1 to BC4 of FIG. 15) provided corresponding to the parallel input terminals PI of the second integrated circuit IC12, and then transferred to the boundary scan cells (corresponding to the boundary scan cells BC5 to BC8 of FIG. 15) corresponding to the parallel output terminals PO of the integrated circuit IC12, whereafter it is outputted from the test serial output terminal TSO. Thereafter, the test data TD is inputted to and outputted from each of the integrated circuits IC13 and IC14 similarly by way of the test serial input terminal TSI and the test serial output terminal TSO.
As the test data TD is outputted by way of parallel signal lines between the parallel output terminals PO of the integrated circuit IC11 and the parallel input terminals PI of the integrated circuit IC12, when, for example, "1111" is inputted as the test data TD, if the parallel signal lines between the parallel output terminals PO of the integrated circuit IC11 and the parallel input terminals PI of the integrated circuit IC12 have some disconnection or some incomplete connection, then the serial data outputted from the test serial output terminal TSO of the second integrated circuit IC12 presents "0" only at the bit or bits thereof corresponding to the failed signal line or lines and is outputted, for example, as data of "1011".
Accordingly, the connection condition between the first and second integrated circuits IC11 and IC12 can be tested based on the output data.
It is to be noted that, while, in actual integrated circuits, for example, also the integrated circuits IC11 and IC13 may be connected to each other or the output of the integrated circuit IC12 may be inputted to the integrated circuit IC11, the circuit system wherein the integrated circuits are connected regularly to each other is shown in FIG. 17 for simplified illustration.
FIG. 18 shows a construction of an electronic apparatus testing system which has been proposed upon introduction of the present invention. In FIG. 18, like elements to those of FIGS. 14 and 15 are denoted by like reference characters. The electronic apparatus shown in FIG. 18 was applied for patent in the United States on Jan. 21, 1993 (U.S. Ser. No. 08/006,760), issued as U.S. Pat. No. 5,390,191 on Feb. 14, 1995, and assigned to the same assignee.
Referring to FIG. 18, an electronic apparatus 20 such as a video tape recorder integrated with a camera includes a pair of integrated circuits IC21 and IC22 on a common circuit board. The parallel output terminals PO of the integrated circuit IC21 are connected to the parallel input terminals PI of the integrated circuit IC22 so that data may be communicated between the integrated circuits IC21 and IC22. The serial interfaces SIF of the integrated circuits IC21 and IC22 are individually connected to a microcomputer COM by way of a selector 23 and an internal communication bus 24 so as to perform serial communication between the microcomputer COM and the integrated circuits IC21 and IC22.
In the electronic apparatus 20 of the construction described above, an external terminal section 25 is connected to the selector 23, and when a select terminal SEL of the external terminal section 25 is controlled to a high ("H") level, the selector 23 is changed over from the microcomputer COM to the external terminal section 25 as indicated by broken lines in FIG. 18.
A testing apparatus 27 is connected to the external terminal section 25 by way of a first bidirectional communication bus 26 such that the testing apparatus 27 transmits various control data to the external terminal section 25 and communicates test data from and to the internal communication bus 24 of the electronic apparatus 20 by way of the external terminal section 25.
An external bus interface 28 is connected to the microcomputer COM, and the testing apparatus 27 is connected to the external bus interface 28 by way of an external communication bus 29 serving as a second bidirectional communication bus. The external communication bus 29 is used for communication of data which are used to remote controller control of the electronic apparatus 20, setting of a mode of the integrated circuits IC21 and IC22, setting of a parameter and so forth, and is particularly used here in order to allow the testing apparatus 27 to transmit to the microcomputer COM a notification to conduct a test. The external bus interface 28 and the external communication bus 29 may be, for example, those called LANC (Local Application Control Bus System: a registered trademark) proposed by the applicant of the present application. Detailed description of the LANC is omitted herein since it is disclosed, for example, in U.S. patent application Ser. No. 4,713,702 assigned to the same assignee.
When the select terminal SEL of the external terminal section 25 is controlled to the "H" level by the testing apparatus 27, the selector 23 is changed over from the microcomputer COM to the external terminal section 25. In this condition, the test serial output terminal TSO, the test serial input terminal TSI and the test clock terminal TCK of the external terminal section 25 are connected to the serial input terminals SI, the serial output terminals SO and the clock input terminals SCK, respectively, of the serial interfaces SIF of the integrated circuits IC21 and IC22.
Further, in this instance, a chip select terminal CSA of the external terminal section 25 is connected to the chip select terminal CS of the integrated circuit IC21, and another chip select terminal CSB of the external terminal section 25 is connected to the chip select terminal CS of the integrated circuit IC22. The integrated circuits IC21 and IC22 are thus caused to operate independently of each other using the two chip select terminals CSA and CSB so that data may not be outputted at a time from the serial output terminals SO of the integrated circuits IC21 and IC22 to the external communication bus 24 connected to the serial interfaces SIF.
Here, the test mode select terminal TMS of the external terminal section 25 is connected to the test mode select terminals TMS of the integrated circuits IC21 and IC22 so that the integrated circuits IC21 and IC22 may be set to a test mode in response to the logic level at the test mode select terminal TMS.
In order to conduct a test, first the chip select terminal CSA of the external terminal section 25 is changed to the "H" level to select the integrated circuit IC21, and the test mode select terminal TMS of the external terminal section 25 is changed to the "H" level to put the integrated circuit IC21 into a test mode. Then, test data is inputted to the serial input terminal SI of the integrated circuit IC21 while a clock signal is inputted to the clock input terminal SCK of the integrated circuit IC21. The test data thus inputted is transferred from the boundary scan cells BC1 to BC4 (not shown in FIG. 18) to the boundary scan cells BC5 to BC8 (not shown in FIG. 18) in synchronism with the clock signal inputted to the clock input terminal SCK of the integrated circuit IC21. In this condition, the chip select terminal CSA of the external terminal section 25 is changed to a low ("L") level to put the integrated circuit IC21 into a hold mode so as to hold the data in the boundary scan cells BC5 to BC8.
Subsequently, the chip select terminal CSB of the external terminal section 25 is changed to the "H"level to select the integrated circuit IC22, and the test mode select terminal TMS of the external terminal section 25 is changed to the "H" level to set the integrated circuit IC22 to a test mode. Then, the integrated circuit IC 22 fetches the data held in the boundary scan cells BC5 to BC8 of the integrated circuit IC21 into the parallel input terminal PI. Subsequently, the test data fetched into the parallel input terminals PI of the integrated circuit IC22 are transferred from the boundary scan cells BC1 to BC4 to the boundary scan cells BC5 to BC8, respectively, of the integrated circuit IC22 and then outputted from the serial output terminal SO of the integrated circuit IC22 in synchronism with a clock signal inputted to the clock input terminal SCK of the integrated circuit IC22.
In the testing system described above, the integrated circuits IC21 and IC22 have no test interface TIF, but each inputs test data at the serial interface SIF thereof. Therefore, each of the integrated circuits IC21 and IC22 requires a switching circuit for sending out, in an ordinary operation mode, data inputted by way of the serial interface SIF to an ordinary signal processing circuit, but sending out, in a test mode, data inputted by way of the serial interface SIF to the boundary scan cells. Meanwhile, since the test interface TIF is eliminated, the integrated circuit is simplified in construction.
However, the electronic apparatus testing system of FIG. 18 requires, in addition to the communication lines for communicating test data between the testing apparatus and the integrated circuits, an additional control signal line for putting the integrated circuits into a test mode. Consequently, where a plurality of integrated circuits are provided in an electronic apparatus, a number of control signal lines equal to the number of integrated circuits are wired on a circuit board, and the circuit board is required to have an additional occupation area for the control lines. Also the external terminal section requires the test mode select terminal TMS for connection to the control signal lines.
Further, since an operation of fetching test data by way of the parallel input terminals of an integrated circuit and another operation of transferring the thus fetched test data are separate from each other, a circuit for realizing such separate operations is required, resulting in complicated construction and increase in size of the integrated circuit.